1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) frequency synthesizer used in a high-frequency multichannel radio or the like and having a high-speed frequency lock function, and a high-speed frequency lock method using this synthesizer.
2. Description of the Related Art
A conventional PLL frequency synthesizer is disclosed in, e.g., Japanese Patent Application Laid-Open No. Hei 1-305724. According to the conventional PLL frequency synthesizer, to realize a high-speed frequency lock operation, a digital signal called from a storage means upon starting the operation is converted into an analog signal, and a potential corresponding to a desired oscillation frequency control voltage of a voltage-controlled oscillator is injected into a loop filter by a potential injecting means.
FIG. 1 is a block diagram showing the PLL frequency synthesizer disclosed in the above application. According to this synthesizer, an output from a reference oscillator 101 is frequency-divided into a 1/M signal output by a frequency divider 102 and input to a phase comparator 103 as a reference signal. On the other hand, an output from a voltage-controlled oscillator 104 for outputting a desired frequency is frequency-divided into a 1/N signal output by a variable frequency divider 105 and input to the phase comparator 103. The phase comparator outputs a phase difference component between the outputs from the frequency divider 102 and the variable frequency divider 105. The output from the phase comparator 103 is input to the control terminal of the voltage-controlled oscillator 104 through a charge pump 106 and a loop filter 107 to control the phase difference with respect to the output from the voltage-controlled oscillator 104. With this operation, a stable output synchronized with the reference signal can be obtained from the voltage-controlled oscillator 104.
To decrease the frequency lock time upon the initial turning on of power or changing of the frequency between channels, the PLL frequency synthesizer also comprises a ROM 110 for outputting a corresponding digital signal on the basis of channel designation data sent from a controller 109, a D-A converter 111 for converting the corresponding signal sent from the ROM 110 into an analog signal, an injection resistor 112 provided to the output circuit of the D-A converter 111, and a changeover switch 113 for switching the operation in accordance with a switching control signal from the controller 109.
In the above-described conventional PLL frequency synthesizer, variations in change in temperature or voltage-controlled oscillator accordingly cause variations the frequency control voltage for a desired frequency. For this reason, a potential in only an approximate range can be applied by the injecting means. This is because the output frequency from the voltage-controlled oscillator largely deviates from the desired frequency upon starting the operation of the PLL frequency synthesizer. In this case, the frequency lock time cannot be sufficiently decreased.